Redundancy in integrated circuit memories is part of current chip manufacturing strategy to improve yield. By replacing defective cells with redundant circuits on chips, integrated circuit memory yields are significantly increased. The practice is to cut or blow conductive connections (fuses) which allow redundant memory cells to be used in place of nonfunctional cells. In the manufacture of integrated circuits, it is also common practice to provide for customization of chips and modules to adapt chips to specific applications. In this way, a single integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Typically, fuses or fusible links are incorporated in the integrated circuit design, and these fuses are selectively blown, for example, by passing an electrical current of sufficient magnitude to cause them to open. An alternative to blowing fuse links with a current is to open a window above the fuses, use a laser to blow the fuses, and then fill the window with a passivating layer. During the fuse blow process, care must be taken to properly align the laser so that the circuit is not damaged by an improperly aimed laser beam.
As circuit density has increased, the number of metallization levels and interlevel dielectric (ILD) levels above the substrate has increased. However, the fuse links usually stay close to the substrate surface (e.g. word line or bit line). Due to the increased total ILD thickness above fuse lines, a well-controlled etch in order to open the fuse window and leave a desired oxide thickness on top of the fuse links is extremely difficult. For example, a fuse etch typically requires etching of 3 .mu.m dielectric layers for a 3 metal layer integrated circuit product (excluding other dielectric such as polyimide). Achieving a .+-.10% etch (i.e. .+-.0.3 .mu.m) uniformity is a very challenging task with existing etch technology.
Several factors contribute to oxide nonuniformity. As more layers of metallization and dielectric layers are employed, pre-etch nonuniformity increases due to nonuniformities from previous process steps such as film deposition, planarization, and etching. The dielectric thickness prior to fuse window etch has been observed to be 3 .mu.m with a variation of .+-.0.2 .mu.m.
In addition, during the fuse window etch the oxide is not uniformly etched. With reactive ion etching (RIE), RIE lag is one cause. When feature sizes differ, RIE lag results in a narrower feature (i.e. narrower "hole" to be etched) to be etched less deeply than a wider feature. Reverse RIE lag is another cause of nonuniformity, in which narrower features are etched more deeply than wider features. Other conditions can cause nonuniformity, and in general the oxide thickness after fuse window etch has been observed to vary from 1000 .ANG. near the edge of the window to 5000 .ANG. near the center of the window.
A uniform fuse oxide is very important. If the oxide is nonexistent, fuse corrosion is a concern; if very thin (i.e. &lt;2000 .ANG.), then fuse cracks are likely which cause yield loss and reliability concerns. Fuse cracks, also called stress cracks, are common at the corner of a fuse window where the oxide tends to be thin. On the other hand, if the oxide is too thick (i.e. &gt;8000 .ANG.) a high laser fusing energy is required to reliably blow the fuse. Furthermore, the laser energy required to blow fuses with thicker oxide, between 7000 and 8000 .ANG., can easily lead to substrate damage, again causing yield loss and reliability concerns. Uniform oxide thickness across the fuse window and within the desired range would be optimal.
In addition, an auxiliary but not unimportant concern with fuse window etching and oxide thickness control is minimization of total etch process time. Another concern is the ability to handle laser misalignment without damaging the surrounding structures or layers.
Thus there remains a need for controlled etching of a fuse window above a fuse link in order to achieve uniform fuse oxide thickness, so that a repeatable, commercially viable fuse blow process can be performed in an integrated circuit production environment.